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october 1999 dsc-3075/04 1 ?1999 integrated device technology, inc. pentium is a trademark of intel corporation. features u u u u u 16k x 15 configuration C 12 tag bits C 3 separate i/o status bits (valid, dirty, write through) u u u u u match output uses valid bit to qualify match output u u u u u high-speed address-to-match comparison times C 8/9/10/12ns over commercial temperature range u u u u u brdy brdy brdy brdy brdy circuitry included inside the cache-tag for highest speed operation u u u u u asynchronous read/match operation with synchronous write and reset operation u u u u u separate we we we we we for the tag bits and the status bits u u u u u separate oe oe oe oe oe for the tag bits, the status bits, and brdy brdy brdy brdy brdy u u u u u synchronous reset reset reset reset reset pin for invalidation of all tag entries u u u u u dual chip selects for easy depth expansion with no performance degredation u u u u u i/o pins both 5v ttl and 3.3v lvttl compatible with v ccq pins u u u u u pwrdn pwrdn pwrdn pwrdn pwrdn pin to place device in low-power mode u u u u u packaged in a 80-pin thin plastic quad flat pack (tqfp). description the idt71215 is a 245,760-bit cache tag static ram, orga- nized 16k x 15 and designed to support the pentium and other intel processors at bus speeds up to 66mhz. there are twelve common i/o tag bits, with the remaining three bits used as status bits. a 12- bit comparator is on-chip to allow fast comparison of the twelve stored tag bits and the current tag input data. an active high match output is generated when these two groups of data are the same for a given address. this high-speed match signal, with t adm as fast as 8ns, provides the fastest possible enabling of secondary cache accesses. the three separate i/o status bits (vld, dty, and wt) can be configured for either dedicated or generic functionality, depending on the sfunc input pin. with sfunc low, the status bits are defined and used internally by the device, allowing easier determination of the validity and use of the given tag data. sfunc high releases the defined internal status bit usage and control, allowing the user to configure the status bit information to fit his system needs. a synchro- nous reset pin, when held low at a rising clock edge, will reset all status bits in the array for easy invalidation of all tag addresses. the idt71215 also provides the option for burst ready ( brdy ) generation within the cache tag itself, based upon match, vld bit, wt bit, and external inputs provided by the user. this can significantly simplify cache controller logic and minimize cache decision time. match and read operations are both asynchronous in order to provide the fastest access times possible, while write operations are synchronous for ease of system timing. the idt71215 uses a 5v power supply on v cc with separate v ccq pins provided for the outputs to offer compliance with both 5v ttl and 3.3v lvttl logic levels. the pwrdn pin offers a low-power standby mode to reduce power consumption by 90%, providing significant system power savings. the idt71215 is fabricated using idts high-performance, high- reliability bicmos technology and is offered in a space-saving 80-pin thin plastic quad flat pack (tqfp) package. pin descriptions a 0 C a 13 address inputs input clk system clock input cs1 , cs2 chip selects input brdyh brdy force high input wet write enable C tag bits input brdyoe brdy output enable input wes write enable C status bits input brdyin additional brdy input input oet output enable C tag bits input brdy burst ready output oes output enable C status bits input tag 0 C tag 11 tag data input/outputs i/o reset status bit reset input vld out /s 1out valid bit/s 1 bit output output pwrdn pow erdown mode control pin input dty out /s 2out dirty bit/s 2 bit output output sfunc status bit function control pin input wt out /s 3out write through bit/s 3 bit output output w/ r write/read input from processor input match match output vld in /s 1in valid bit/s 1 bit input input v cc +5v power pwr dty in /s 2in dirty bit/s 2 bit input input v ccq output buffer power qpwr wt in /s 3in write through bit/s 3 bit input input v ss ground gnd 3075 tbl 01 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor idt71215
6.42 2 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range pin configuration tqfp top view 3075 drw 01 pn80-1 v ss v ss 80 1 a 8 t a g 1 v s s d t y o u t /s 2 o u t b r d y in b r d y h w / r v s s s f u n c v ld in /s 1 in t a g 9 t a g 10 v s s t a g 11 b r d y o e o e t o e s c lk r e s e t v s s v c c w e s w e t c s 1 c s 2 p w r d n v s s v c c v ss v ss v ss nc tag4 tag5 wt out /s3 out v ss match brdy v ss vld out /s1 out tag6 tag7 tag8 v ss v ss v ss v ss v ss v ss a7 a6 a5 a4 a3 v ss v cc a2 a1 a0 wt in /s3 in dty in /s2 in v ss v ss v ss v s s v ccq v ccq v c c q v c c q t a g 0 t a g 2 t a g 3 v c c a 9 a 10 a 11 a 12 a 13
6.42 3 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range functional block diagram clk sfunc addr (0:13) vld/s1 out dty/s2 out wt/s3 out reset wet wes 16k x 12 memory tag bits tag (0:11) oet 16k x 3 memory status bits match brdyh w/ r brdyoe brdy brdyin vld/s1 in dty/s2 in wt/s3 in sa cs2 cs1 reset (neg) pulse generator pwrdn data in register data in register write (pos) pulse generator sa compare reg 0 1 oes reg reg reg 3075 drw 02
6.42 4 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range truth table ? chip select, reset, and power-down functions (1,2) notes: 1. "h" = v ih , "l" = v il , "x" = don't care, "C" = unrelated. 2. oet , oes , w/ r , brdyh, brdyin and sfunc are "x" for this table. 3. oes is low. notes: 1. "h" = v ih , "l" = v il , "x" = don't care, "C" = unrelated. 2. this table applies when cs1 is low and cs2, reset , and pwrdn are high. brdyoe , brdyh, brdyin and sfunc are "x" for this table. 3. d out in this case is the same as d in ; that is, the input data is written through to the outputs during the write operation. c s 1 cs2 r es e t p w r d n clk w e t w e s b r d y o e tag vld out dty out wt out match b r d y operation power chip select function h x x h x x x x hi-z hi-z hi-z hi-z hi-z hi-z deselected active x l x h x x x x hi-z hi-z hi-z hi-z hi-z hi-z deselected active lh x h xxx x selected active reset function lh l h - hh l hi-zl (3 ) l (3 ) l (3 ) l (3 ) h reset status active lh l h - hh h hi-zl (3 ) l (3 ) l (3 ) l (3 ) hi-z reset status active hx l h - h h x hi-z hi-z hi-z hi-z hi-z hi-z reset status active xl l h - h h x hi-z hi-z hi-z hi-z hi-z hi-z reset status active xx l h - lx x not allowed xx l h - xl x not allowed power-down function x x x l x h h x hi-z hi-z hi-z hi-z hi-z hi-z power-down standby 3075 tbl 02 o e t o e s w e t w e s clk w/ r tag vld in dty in wt in vld out dty out wt out match operation read function lx h x xx d out d out read tag i/o xlx xxx d out d out d out d out read status bits hx x x xx hi-z d out tag i/o disable x h x x x x hi-z hi-z hi-z d out status disabled write function hx l x - xd in d out d out d out l write tag i/o lx l x - x not allowed xlx l - xd in d in d in d out (3) d out (3) d out (3) l write status bits xhx l - xd in d in d in hi-z hi-z hi-z l write status bits 3075 tbl 03 truth table ? read and write functions (1,2)
6.42 5 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range truth table ? match function (1,2,3) notes: 1. "h" = v ih , "l" = v il , "x" = don't care, "C" = unrelated. 2. m = high if tag in equals the memory contents at that address; m = low if tag in does not equal the memory contents at that address. 3. pwrdn and reset are high for this table. clk and oes are "x". 4. this column represents the stored memory cell data for the given status bit at the selected address. 5. cs1 is low, cs2 is high for this table. 6. brdyin is a synchronous input; thus the inputs noted in the table must be applied during a rising clk edge. 7. brdyin will be a factor in determining the brdy output in all cases except when brdyh is high and there is a valid match. in that case, brdy will be low(valid). notes: 1. "h" = v ih , "l" = v il , "x" = don't care, "C" = unrelated. 2. m = high if tag in equals the memory contents at that address; m = low if tag in does not equal the memory contents at that address. 3. pwrdn and reset are high for this table. w/ r , brdyh, brdyoe , brdyin , oes , and clk are "x". 4. this column represents the stored memory cell data for the given status bit at the selected address. c s 1 cs2 sfunc o e t w e t w e s tag vld (4 ) dty (4 ) wt (4 ) match operation h x x x x x hi-z hi-z deselected x l x x x x hi-z hi-z deselected lh x x xx d out selected lh x l hx d out l read tag i/o lh x h lx d in l write tag i/o lh x x xl d in d in d in l write status bits lh l h hh tag in l l invalid data dedicated status bits lh l h hh tag in h m match dedicated status bits lh h h hh tag in x m match generic status bits 3075 tbl 04 b r d y o e b r d y i n (6 ) o e t w e t w e s brdyh w/ r sfunc vld (4 ) dty (4 ) wt (4 ) tag match b r d y operation hxxxxxxx xxhi-z brdy disabled llxxxxxx xxxlext brdy input (7 ) lhlxxxxx xxd out l h read tag lhxlxxxx xxd in lh write tag lhxxlxxxd in d in d in l h write status lhxxxhxx xxxhforce brdy high lhxxxxxl lxlhinvalid tag l h x x x x h l x h x h write through lhhhhlxl hltag in m m compare lhhhhlll hxtag in m m compare lhhhhlxl hxtag in m m compare lhhhhlxh xxtag in m m compare 3075 tbl 05 truth table ? brdy function (1,2,3,5)
6.42 6 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range symbol parameter (1 ) condition max. unit c in input capacitance v in = 0v 5 pf c tag tag input/ouput capacitance v i/o = 0v 7 pf c out output capacitance v out = 0v 7 pf 3075 tbl 07 symbol parameter min. typ. max. unit v cc supply voltage 4.75 5.0 5.25 v v ccq 5v output buffers 4.75 5.0 5.25 v v ccq 3.3v output buffers 3.0 3.3 3.6 v v ss supply ground 0 0 0 v v ih input high voltage 2.2 3.0 v cc +0.3 v v ihq i/o high voltage 2.2 3.0 v ccq +0.3 v v il input low voltage C0.5 (1 ) 0.8v 3075 tbl 06 dc electrical characteristics over the operating temperature and supply voltage range (1,2) (v cc = 5.0v 5%) capacitance (t a = +25c, f = 1.0mhz) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. v in should not exceed vcc+0.5v. all pins should not exceed 7.0v. v ccq should never exceed v cc , and v cc should never exceed v ccq + 4.0v. note: 1. v il (min.) = C1.5v for pulse width of less than 10ns, once per cycle. recommended dc operating conditions note: 1. this parameter is determined by device characterization but is not production tested. dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 5%, v ccq = 5.0v 5% or 3.3v 0.3v) notes: 1. all values are maximum guaranteed values. 2. cs1 v il , cs2 3 v ih . 3. f max =1/t cyc (all address inputs are cycling at f max ). f = 0 means no address input lines are changing. 4. v hc = v cc - 0.2v, v lc = 0.2v absolute maximum ratings (1) symbol rating value unit v term terminal voltage with respect to gnd C0.5 to + 7.0 (2 ) v t a operating temperature 0 to +70 c t bias temperature under bias C65 to +135 c t stg storage temperature C65 to +150 c p t power dissipation 1.7 w i out dc output current 20 ma 3075 tbl 08 symbol parameter test condition min. max. unit |i li | input leakage current v cc = max., v in = 0v to v cc 5 |i lo | output leakage current cs1 3 v ih , cs2 v il , oe 3 v ih , v cc = max. v out = 0v to v ccq , v ccq = max. 5a v ol output low voltage i ol = 4ma, v cc = min. 0.4 v v oh output high voltage i oh = C4ma, v cc = min. 2.4 v 3075 tbl 09 symbol parameter test condition 71215s8 71215s9 71215s10 71215s12 unit com'l. mil. com'l. mil. com'l. mil. com'l. mil. i cc operating power supply current pwrdn 3 v ih outputs open, v cc = max., f = f max (3 ) 330 300 290 280 ma i sb standby power supply current pwrdn v il , v in 3 v ih or v il v cc = max., f = f max (3 ) 30 30 30 30 ma i sb1 full standby power supply current pwrdn v il , v in 3 v hc or v lc (4 ) v cc = max., f = 0 (3 ) 25 25 25 25 ma 3075 tbl 10
6.42 7 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range note: 1. this parameter is guaranteed with the ac load (figure 3) by device characterization, but is not production tested. ac electrical characteristics (v cc = 5.0v 5%, v ccq = 5.0v 5% or 3.3v 0.3v, t a = 0 to 70c) symbol parameter idt71215s8 idt71215s9 idt71215s10 idt71215s12 unit min. max. min. max. min. max. min. max. read cycle t aat address access time tag bits 10 11 12 14 ns t acst chip select access time tag bits 8 9 10 12 ns t clz (1 ) chip select to tag and status bits in low-z 1 1 1 1 ns t chz (1 ) chip select to tag and status bits in high-z 1 5 1 6 1 6 1 7 ns t oet output enable to tag bits valid 5 6 6 7 ns t otlz (1 ) output enable to tag bits in low-z 0 0 0 0 ns t othz (1 ) output enable to tag bits in high-z 1 5 1 6 1 6 1 7 ns t toh tag bit hold from address change 2 2 2 2 ns t oes output enable to status bits valid 5 6 6 7 ns t os lz (1 ) output enable to status bits in low-z 0 0 0 0 ns t oshz (1 ) output enable to status bits in high-z 1 5 1 6 1 6 1 7 ns t aas address access time status bits 8 9 10 12 ns t acss chip select access time status bits 6 7 8 10 ns t soh status bit hold from address change 2 2 2 2 ns 3075 tbl 11
6.42 8 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range symbol parameter idt71215s8 idt71215s9 idt71215s10 idt71215s12 unit min. max. min. max. min. max. min. max. reset and power down cycles t sr reset set-up time 4444ns t hr reset hold time 1 1 1 1ns t srst status bit reset time 50 60 60 70 ns t shrs status bit hold from reset low 2222ns t rsmi reset low to match and brdy invalid 9 101012ns t rsm v reset high to match and brdy valid 110 120 120 130 ns t rshz (2 ) reset low to tag high-z 9 101012ns t rslz (2 ) reset high to tag low-z 90 100 100 110 ns t pdsr pwrdn set-up to reset low 30 30 30 30 ns t rhpl reset high to pwdrn low 1 1 1 1clk t rhwl reset high to wet and wes low 90 95 95 105 ns t pd (2 ) pwrdn low to low power mode 50 50 50 50 ns t pu (2 ) pwrdn high to active power mode 0000ns t pdhz (2 ) pwrdn low to outputs in high-z 9 101012ns t pdlz (2 ) pwrdn high to outputs in low-z 0000ns t puv pwrdn high to outputs valid 50 50 50 50 ns t whpl (2 ) wet and wes high to pwrdn low 5555ns t puwl pwrdn high to wet and wes active 50 50 50 50 ns 3075 tbl 12 ac electrical characteristics (1) (v cc = 5.0v 5%, v ccq = 5.0v 5% or 3.3v 0.3v, t a = 0 to 70c) notes: 1. power-down mode is intended to be used during extended time periods of device inactivity. 2. this parameter is guaranteed with the ac load (figure 3) by device characterization, but is not production tested.
6.42 9 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range ac electrical characteristics (1) (v cc = 5.0v 5%, v ccq = 5.0v 5% or 3.3v 0.3v, t a = 0 to 70c) notes: 1. all write cycles are synchronous and referenced from rising clk. 2. this parameter is measured as a high time above 2.0v and a low time below 0.8v. 3. this parameter is guaranteed with the ac load (figure 3) by device characterization, but is not production tested. 4. addresses are stable prior to clk transition high. symbol parameter idt71215s8 idt71215s9 idt71215s10 idt71215s12 unit min. max. min. max. min. max. min. max. write cycle and clock parameters t cyc clock cycle time 15 15 15 16.6 ns t ch (2, 3) clock pulse high 4.5 4.5 4.5 5 ns t cl (2, 3) clock pulse low 4.5 4.5 4.5 5 ns t s wet , wes , chip select, and input data set-up time 3333ns t h wet , wes , chip select, and input data hold time 1 1 1 1ns t sa address set-up time 3 3 3 3 ns t ha address hold time 1 1 1 1 ns t wm i clk high write to match and brdy invalid 6778ns t cklz (3 ) clk high read to outputs in low-z 1.5 1.5 1.5 1.5 ns t ctv (4 ) clk high read to tag bits valid 9 10 10 12 ns t csv (4 ) clk high write to status outputs valid 8 9 9 10 ns t csh (3 ) status output hold from clk high write 0 0 0 0 ns t whpl wet and wes high to pwrdn low 5555ns t puwl pwrdn high to wet and wes active 50 50 50 50 ns 3075 tbl 14
6.42 10 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range notes: 1. this parameter is guaranteed with the ac load (figure 3) by device characterization, but is not production tested. 2. these parameters only apply when sfunc is low and the internal wt bit is high. 3. t adm , t dam , t csm and t adb , t dab , t csb must also be satisfied. ac electrical characteristics (v cc = 5.0v 5%, v ccq = 5.0v 5% or 3.3v 0.3v, t a = 0 to 70c) symbol parameter idt71215s8 idt71215s9 idt71215s10 idt71215s12 unit min. max. min. max. min. max. min. max. match and b r d y cycles t adm address to match valid 8 9 10 12 ns t dam data input to match valid 8 9 10 12 ns t csm c hip select to m atch valid 8 9 10 12 ns t cm lz (1 ) chip select to match in low-z 1 1 1 1ns t cmhz (1 ) chip select to match in high-z 1 5 1 6 1 6 1 7 ns t mha match valid hold from address 2222ns t mhd m atch valid hold from data 2 2 2 2 ns t bha brdy valid hold from address 2222ns t bhd brdy valid hold from data 2222ns t adb address to brdy valid 9 10 11 13 ns t dab data input to brdy valid 9 10 11 13 ns t csb chip select low to brdy valid 9 10 11 13 ns t oebv brdyoe low to brdy valid 6678ns t oblz (1 ) brdyoe low to brdy in low-z 0000ns t obhz (1 ) brdyoe high to brdy in high-z 15 16 16 17ns t byfh brdyh high to force brdy high 5556ns t byhv brdyh low to brdy valid 5556ns t sb brdyin set-up time 4444ns t hb brdyin hold time 1.5 1.5 1.5 1.5 ns t bibl clk high brdyin low to brdy low 6678ns t bibv clk high brdyin high to brdy valid 6678ns t oemi oet low to match and brdy invalid 6778ns t oemv oet high to match and brdy valid 78810ns t wrbh (2 ) w/ r high to brdy high 6778ns t wrb v (2 ) w/ r low to brdy valid 6778ns t wm i clk high write to match and brdy invalid7778ns t wm v (3 ) clk high read to match and brdy valid 891012ns 3075 tbl 15
6.42 11 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output timing reference levels 1.5v ac test load see figures 1, 2, 3, & 4 3075 t bl 16 ac test loads ac test conditions figure 4. lumped capacitance load, typical derating figure 1. ac test load figure 3. ac test load (for t hz and t lz parameters ) * including scope and jig capacitance figure 2. tag i/o ac test load outputs v ccq 30pf * 3075 drw 03 893 w 347 w tag i/o v ccq 50pf * 3075 drw 04 893 w 347 w v ccq 5pf* 3075 drw 05 tag i/o and outputs 893 w 347 w 1 2 3 4 20 30 50 100 3075 drw 06 d t (typical, ns) d capacitance (pf) 80 5 6 * including scope and jig capacitance
6.42 12 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range timing waveforms of write and read cycles note: 1. transition is measured 200mv from steady state. c lk a (0:13) t a g (0:11) v ld in d t y in w t in v ld o u t d t y o u t w e s w e t o e t c s 1 c s 2 w t o u t t a a t v alid input v alid v alid o utput t c s v t c t v t a a t t h t s t h t s t a c s s t c lz (1) t c k lz (1) t o t h z (1) t o e t t o tlz (1) t c h z (1) v a lid v a lid v alid o u tp u t v a lid t a c s t t c lz (1) t c h z (1) t s o h v alid o u tp u t t a a s t t o h t s t h s t a t u s w r it e t a g w r it e t a g r e a d t s o h t a a s t h t s v alid v alid v alid v alid 3075 drw 07 t c s h
6.42 13 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range timing waveforms of match and brdy functions note: 1. transition is measured 200mv from steady state. v alid v alid b r d y c lk a (0:13) t a g (0:11) w e s w e t o e t b r d y h b r d y o e b r d y m a t c h c s 1 c s 2 m a t c h v alid t m h a t d a m t b y f h t b y h v t w m i t w m v t o e m i t o e m v t c m h z (1) t c m lz (1) t w m i t w m v t a d m t m h d v alid t o b lz (1) t o e b v v alid v alid t d a b t a d b t c s m v alid v alid t o b h z (1) t c s b v alid v alid v alid v alid a ddress v alid m atch d ata t s t h t s t h t s t h t s v alid 3075 drw 08 t b h d t b h a
6.42 14 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range timing waveforms of reset function note: 1. transition is measured 200mv from steady state. clock timing waveform timing waveforms of brdy and w/ r signal vld out dty out wes wet brdy match reset pwrdn wt out clk tag (0:11) t rsmv t pdsr t sr t s t rsmi t rhwl t hr valid valid t rslz (1) t rshz (1) t shrs t srst 3075 drw 09 t cyc t ch t cl clk 0.8v 2.0v 2.0v 0.8v 3075 drw 10 w/ r brdy brdyin clk applies when sfunc is low, and the internal wt bit is high t wrbh t wrbv brdy valid brdy valid t bibl t bibv t sb t hb 3075 drw 11
6.42 15 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range timing waveforms of oes function note: 1. transition is measured 200mv from steady state. timing waveforms of power down function ordering information note: 1. transition is measured 200mv from steady state. tag (0:11) vld out dty out wet , wes reset brdy match pwrdn wt out clk i cc i sb t whpl t puwl t puv t pd t pu valid tag out valid status out brdy valid match valid t s t s 3075 drw 13 t pdlz (1) t pdhz (1) t rhpl idt 71215 pf xx 8 9 10 12 speed in nanoseconds 3075 drw 14 s device type package pf plastic thin quad flatpack (pn80-1) power speed vld out dty out wt out oes t oshz (1) t oes t oslz (1) valid output valid output 3075 drw 12
6.42 16 idt71215 bicmos static ram 240k (16k x 15-bit) cache-tag ram for the pentium? processor co mmercial temperature range datasheet document history corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726, x4033 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. 10/19/99 updated to new format pg. 15 added datasheet document history

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